‘End of an Era: How Silicon Will Decide BIM’s Future’ will run on Architosh on 24 December 2025. The feature first ran in our Xpresso-4X newsletter published today (18 December). To gain early access to some of our best content, subscribe to Xpresso-4X now. It’s free!
THIS COMPANION FEATURE is exclusively for INSIDER subscribers only and covers our extensive research and notes behind the Special Feature, “End of an Era: How Silicon Will Decide BIM’s Future,” published in our Xpresso-4X newsletter today.
Extensive Research
The research for this newest feature was the most in-depth and extensive writing process in the publication’s history. Moreover, we intend to do more extensively researched features like this in the future. While the above feature includes a few link-outs, this article lists over 40 sources and includes extensive notes from academic and technical resources behind paywalls.
Sources are also further annotated in some cases, and this article includes images not found in the main feature.
Annotated Citations
The article’s main sections organize the following citations (link-outs). Readers are free to write in to the editor at anthony {at} architosh {dot} com for personal questions or comments.
The Assumptions CAD and BIM Were Built On
CAD and BIM applications from the beginning are inherently sequential in their core CAD operations (functions). Therefore, they have historically been difficult to parallelize across multiple cores, and most of the industry’s heavyweights were founded before multicore CPUs existed. Generally speaking, a CAD user experiences the speed of a CAD application when moving drawings or models around to work on a single area. Hence, drawing, regeneration, panning, and zooming have historically been sequential and single-threaded.
Another factor in 3D geometric models is constraint solving. When you move a component in a complex assembly, the software must recalculate all the physical and geometric relationships and constraints in sequence to ensure the model remains coherent.
Because the majority of user-facing interactive tasks in CAD and BIM programs has been traditionally bottlenecked by a single sequence of instructions, the most valuable performance metric for a CAD workstation has been the speed at which a single CPU core could execute work. This is measured in IPC (instructions per clock) multiplied by the chip’s clock frequency.
(1) Processors for CAD Hardware: Find the Balance Between Multiple Cores and Increased Single-Thread Performance — (Cadalyst)
(2) Understanding CPU Cores vs Clock Speed for CAD: What Really Matters for Performance — Landmark Computers
Additional articles that discuss the CAD industry and how chips relate to the code behind BIM and CAD include “Matching workstations to real-world workflows” by AEC Magazine and “Intel Core vs AMD Ryzen for CAD, BIM & beyond” by AEC Magazine’s Greg Corke.
(3) BOXX Solutions Guide for Revit Workstations — BOXX Computers
(4) The Shifting Semiconductor Landscape: Intel Arm, AES, Apple, Microsoft, Qualcomm, MediaTek, NVIDIA, AMD, and Beyond. – Medium
When x86 Met Physics (High-Frequency Era)
While much of Intel’s 10nm node manufacturing problems have been blamed on the company’s decision to remain with DUV lithography versus adopting the then-emerging EUV lithography equipment from ASML, the fundamental issue is still one of colliding with physics.
By pushing for transistor density at aggressive levels, the wiring inside Intel’s 10nm chips had such tight pitches (the gap between wires) that increased wire resistance emerged, complicating timing and increasing sensitivity to process variability. Both of those are concrete manifestations of the physical limits mentioned in the core article. (see 8 – 9 below).
The solution to Intel’s 10nm debacle was to lower headroom voltage and frequencies. Cannon Lake and Ice Lake families were notably lower than even older 14nm parts, despite healthy IPC gains on Ice Lake. Cannon Lake ran at 2.2 GHz base with 3.2 GHz turbo cores, while Skylake through Coffee Lake (14nm mature nodes) shipped at base clocks around 3.6 – 4.0 GHz. Intel’s 10nm chips could not sustain the same frequencies as the previous generation.
(5) Intel’s 10nm Is Broken, Delayed Until 2019 – Tom’s Hardware
This article talks about how Intel bit off a little too much by increasing density 2.7X over the 14nm node, where in the step up to 14nm, Intel increased density by 2.4x.
(6) Mapping Intel’s Tick Tock Clock Onto Xeon Processors — New Platform
This is a great article because it notes that when Dennard scaling (see next citation) ran out of gas (I think at 90nm node), Intel, AMD, IBM, and other chip makers needed to increase parallelism rather than ever-faster clock speeds to eke out performance gains. When Dennard scaling ended, Intel shifted to the famous Tick Tock philosophy. A tick was a shrink to a new (smaller) manufacturing process, and the Tock was a shift to a new chip architecture with expected marginal improvements in IPC (instructions per clock).
It’s critical to note that Tick-Tock finally broke down for Intel at 14nm. Intel originally planned to use the 10nm node for a three-stage process. It is called “Process (Tick)-Architecture (Tock)-Optimization.” Now, even rivals like TSMC span a chip node across four or more generations of improvements (e.g., TSMC’s 5nm family, from N5, N5P, N4, N4P, N4X). This allows a chip manufacturer to tune performance gains via adjustments to density, architecture, power, and tuned PDKs (Process Design Kits).
(7) Dennard Scaling – Wikipedia Entry
This article discusses the physics of Dennard Scaling. A bit technical for the average reader, you can use Google Gemini or another AI chatbot to explain it in simpler or alternative terms. Moore’s law itself—which states that the number of transistors on a microchip doubles approximately every two years—is here at Wikipedia.
The next set of citations reviews the more specific physics challenges Intel encountered at 10nm, focusing on gate, metal, and fin pitches, as well as problems with the metal interconnect layers and timing closure. These issues are highly related to the argument that at 10nm, Intel collided with physics. In the end, Intel had to lower the frequencies of its 10nm chips to get acceptable yields. To understand this, “pitch” in semiconductor language refers to the distances between features in a chip.
Metal pitch refers to the minimum center-to-center distance between adjacent parallel metal interconnect lines on a chip. The metal layers form the “wiring” that connects all the transistors and components of the chip. Gate pitch is the minimum center-to-center distance between adjacent transistor gates.
Intel’s 10nm process targeted a very aggressive minimal metal pitch of just 36nm. In comparison, TSMC’s 7nm node had a less aggressive pitch of around 40nm.
(8) Intel’s 10nm Node: Past, Present, and Future — EE Times
This is a comprehensive 2020 review looking back at Intel’s 10nm node nightmare, and it is also important because the article describes how Intel shifted from copper to cobalt for the lowest metal interconnect layers to address the higher resistance expected from the tighter metal pitch.
“The shrinking geometries, in turn, place elevated demands on the metallization process and typical yield-related fail modes include incomplete gap-fill or voiding,” said Nicolas Breil, director of technical projects at Applied Materials, in an IEDM presentation two years ago.
This partial use of cobalt is described in Intel’s IEDM 2017 10nm paper, which states that cobalt was introduced to improve electromigration and resistance.
(9) Timing Closure Issues Resurface — Semiconductor Engineering
This article discusses how timing closure had resurfaced as a major challenge at 10nm and 7nm due to features and power modes, increased process variation, and other manufacturing error issues.
(10) Cobalt Could Untangle Chip’s Wiring Problems — IEEE Spectrum
This article’s opening sentence captures perfectly how Intel and other chip makers are colliding with the laws of physics.
“Today’s computer chips contain tens of kilometers of copper wiring, built up in 15 or so layers. As the semiconductor industry has shrunk the size of transistors, it has also had to make these interconnects thinner.”
And here is another pivotal quote that supports the case that Intel collided with physics:
“The problem they’re trying to solve stems from basic physics: The narrower a wire (and the longer it is), the higher its electrical resistance. “Scaling is always bad for wires,” says Daniel Edelstein, a research fellow at the IBM Thomas J. Watson Research Center, in Yorktown Heights, N.Y. One of the chief architects of the technology that allowed IBM to switch from aluminum to copper in 1997, Edelstein knows his interconnects.”
The next set of citations reviews the more specific physics challenges Intel encountered at 10nm, without necessarily addressing Intel in each case. DUV multi-patterning challenges, DUV versus EUV, and the important wiring shrink issues are covered.
(11) EUV vs DUV Native Defect Levels: Baseline Comparison — Eureka
This article describes the “process variability” inherent to lithography processes, comparing Extreme Ultraviolet (EUV) and Deep Ultraviolet (DUV) lithography technologies. Intel took DUV to an extreme level, with 4-6 lithography passes (complex, multi-layered patterning) to achieve the tiny 3D features of its chip design. But one naturally occurring defect native to the lithography process is tool precision. For example, lens aberrations can lead to incorrect feature creation.
This article at Wikipedia also covers process defects from EUV stochastic issues to mask defects to lens variation issues.
(12) EUV’s Future Looks Even Brighter — Semiconductor Engineering
This article discusses how EUV improves pattern fidelity and reduces some overlay and line‑edge variability versus multi‑patterned DUV, but also emphasizes ongoing challenges with resist stochastic defects, mask contamination, and dose/process‑window tightness at leading nodes
(13) How To Reduce Timing Closure Headaches – Semiconductor Engineering
The Voltage-Limited Era Arrives
(14) The Incredible Shrinking Transistor — Bits and Bytes (Substack)
This article is a historical overview of the history of shrinking the transistor. An important note about this article is that it clarifies that at every 10X increase in transistor count, a new class of computer are built upon that technology. This scaling law, related to Moore’s Law, has held true from Mainframes to Minicomputers to Microcomputers to Workstations, Desktops, Laptops, Smartphones, to Datacenters, to AI computers.
(15) ARM vs x86: The Future of competing computing architecture — Versus
A good overview article written in an easy-to-understand and friendly tone. Its accuracy is pretty solid, but its characterization of x86 as the performance king is misleading, especially since the Apple M1 has held the single-core performance crown for several years, with one brief moment now where they didn’t.
(16) Intel: Confronting Shifts and ARM’s Dominance — Seeking Alpha
This article is actually the second in a series, with the first article discussing Intel’s upcoming products and strategy moving forward. A key takeaway from this article is in the title and in the fact that market analysts acknowledge ARM’s dominance in key sectors of the chip industry (mobile PCs, the hyperscalers, and certain data center segments).
(17) The Tectonic Shift: Why ARM Is Reshaping Computing — Medium
This is a very good article that makes note from the beginning that ARM is proving it can beat x86 in both power and efficiency. That doesn’t mean performance per watt—that’s what “efficiency” means. Both Apple and Qualcomm have shown that ARM can win at power (performance) over x86 as well. Another key mention (and metric) mentioned in this article that speaks to both consumer PCs and datacenters is cost:
“While power efficiency is often the headline, cost is an equally important factor. Apple’s M-series chips aren’t just fast — they make MacBooks more efficient, giving Apple better margins while improving user experience. AWS’s Graviton ARM servers allow companies to cut cloud costs, making x86 instances look overpriced. Qualcomm and Microsoft are pushing ARM into Windows laptops, promising better battery life at lower prices.”
The article does make a crucial mistake, especially as related to the CAD and BIM industry, with its single-threaded software prevalence, noting that x86 still dominates performance. That is simply factually not true. Another key note in this piece is the mention of AMD’s earlier ARM plans.
“AMD’s current ARM push isn’t their first rodeo. Back in 2014–2016, the company had ambitious plans for ARM integration that were arguably ahead of their time. The K12 project promised custom ARM cores that could deliver x86-level performance, while Project Skybridge aimed to create pin-compatible x86 and ARM SoCs that manufacturers could swap interchangeably.”
Another great note in this article is the comment that market dynamics are forcing an interesting stand-off for Intel and AMD:
“Both companies have spent decades building their x86 empires, but ARM’s accelerating momentum has forced them into an uncomfortable position: choose between preserving market share or preserving architecture loyalty.”
This is critical because nothing is preventing AMD and Intel from designing their own ARM chips. Finally, it’s worth quoting this article’s final thoughts:
“The ARM vs. x86 battle isn’t just a technical rivalry — it’s a fundamental industry shift driven by efficiency, cost, and the changing needs of modern computing.
Intel and AMD built an empire that lasted decades. But the world has changed, and the question now isn’t whether ARM can compete — it’s whether x86 can survive the new reality. The acceleration of this shift means we’re likely to see dramatic moves from both companies much sooner than expected — possibly within the next year or two.
The computing industry’s next chapter is being written, and for the first time in decades, the ending isn’t predetermined.”
Apple Silicon Changed the Conversation
(18) Steve Jobs’s last gambit: Apple M1 Chip — OM
Written shortly after the debut of the M1 back in the fall of 2020, this excellent perspective piece really peers into the future with smart observations. Like this one:
“I don’t think AMD and Intel are Apple’s competitors. We should be looking at Qualcomm as the next significant laptop chip supplier. Apple’s M1 is going to spark an interest in new architectures from its rivals. “
The author also emphasizes that the future of computing is heterogeneous and machine learning (ML) will define the capabilities of the software of the future.
(19) Apple M1 Chip Turns 5: How It Transformed Computing Forever — Gadget Hacks
(20) Impacts of Apple’s M1 SoC on the Technology Industry — Peer-Reviewed Paper (PDF)
Qualcomm Proved It Wasn’t Just Apple
(21) Snapdragon X Long-Term Review: Lenovo Laptop Wins As A Daily Driver — Forbes
This general review notes Snapdragon’s performance characteristics, even under battery model, which is a hallmark feature of ARM chips. Cinebench was used for benchmarking against AMD and Intel competition. Qualcomm’s latest X2 Elite is the first ARM consumer chip over 5 GHz (see Snapdragon Summit 2025).
(22) Choosing the Right AI Laptop: Snapdragon X Elite vs AMD Ryzen AI vs Intel Core Ultra — HP Blog
HP itself makes all three kinds of laptops and does a good comparison in business general terms. One key thing it highlights is the battery life system. Both AMD and Intel mobile computers get about 12-16 hours of run time. The Snapdragon X Elite HP mobile computer gets 20-34 hours. That’s the kind of energy efficiency ARM chips offer.
Hyperscalers Follow the Physics
(23) Introducing Google’s first Arm-based CPU: Google Axion — Google
From 2024, this announcement shows that Google built the Axion using an Arm Neoverse V2 CPU at its core. Axion is a SoC like Apple Silicon but oriented for datacenter needs. A key statement made by Google in this article is:
“Amdahl’s Law suggests that as accelerators continue to improve, general-purpose computing will dominate the cost and limit the capability of our infrastructure unless we make commensurate investments to keep up.”
Amdahl’s Law is a formula that states the maximum speedup of a program is limited by the fraction of the program that cannot be parallelized (the serial portion). What this means in the context of the data center is that the general-purpose CPU is becoming the serial portion that holds back the total system performance and efficiency. The hyperscalers are therefore investing heavily in specialized parallel accelerators: the GPU for training and the NPU for inference.
(24) From Cloud to Edge, Why Arm is Built for Scaling Your AI Stack — Arm
(25) How Arm is Winning Over AWS, Google, Microsoft, and Nvidia In Data Centers — CRN
(26) Half of Compute Shipped to Top Hyperscalers in 2025 will be Arm-based — Arm
Intel’s Countermove: 18A and Backside Power Delivery
(27) Intel 18A: See Our Biggest Process Innovation – Intel
(28) Device Engineering: Where Ambitions and Real Silicon Collide – Intel
This is an interesting article because it talks about how Intel flipped the fins of RibbonFET on their sides to stake them with gate-all-around. It also mentions that the fins are just 10nm apart. That doesn’t necessarily correspond to fin pitch (which is center to center), though it could possibly be the case. Here’s a quote:
“What makes the RibbonFET hard to make is its three-dimensional intricacy. To peek into just one slice of it: Materials that form the suspended horizontal ribbons are layered across the entire bare silicon wafer first – and then etched away except where ribbons are needed. New layers are added, trenches are etched, and new materials are deposited in precise locations, sometimes atom by atom.”
(29) Intel details 18A process technology — takes on TSMC 2nm — Tom’s Hardware
(30) – Can Intel’s 18A Break TSMC’s 2nm Stronghold? – Nasqaq
Written in June of 2025, this article looks more at the business side of Intel’s 18A process node and foundry model and its technology in comparison to TSMC and Samsung. An interesting note in this article is that even Intel is hedging its bets, sort of speak, by getting on the TSMC docket as a second source for some of its upcoming Nova Lake desktop processors, expected in 2026.
While Intel’s 18A process node is delivering not one but two groundbreaking innovations, it remains to be seen whether actual chips will outperform the competition from AMD, Apple, and Qualcomm, and whether Intel will beat TSMC and Samsung to market in 2026.
(31) – Nvidia and AMD plan to launch Arm PC chips as soon as 2025, Reuters reports – The Verge
While the year is not over, this looks to not be happening, especially for Nvidia. However, a fresh story may indicate an upcoming AMD ARM chip. The story over at PCGames says that a new AMD ARM Ryzen chip has been spotted in shipping manifests.
(32) Softbank to invest $2bn in Intel as US gov’t continues to mull plans for stake of its own — DCD
SoftBank owns most of ARM and recently acquired chipmaker Ampere Computing. Along with OpenAI, Oracle, and Abu Dhabi’s MGX, SoftBank is a major financial partners in OpenAI’s $500 billion AI data center effort dubbed Project Stargate. And Oracle is a major customer of Ampere Computing’s ARM chips for data centers. All of this suggests that Intel Foundry may have future customers in both Ampere and ARM itself, as it, too, is moving forward with plans to build out its own server chips.
(33) Apple and Intel are reportedly set to rekindle their chip partnership — Macworld
Industry analyst Ming-Chi Kuo revealed on Twitter/X that Intel is now expected to take a role within Apple’s chip supply chain within two years. If true, this would very much signal that Intel’s Foundry Services has found its first mega customer. SoftBank’s investment in Intel would then signal that Ampere Computing would also go to Intel to produce its ARM server chips, as well as future chips from ARM in the UK itself.
What This Means for BIM and CAD
(34) The primary reason why Microsoft is pushing ARM architecture for Windows is to diversify its chip supply, improve power efficiency and battery life, drive the new “AI PC” era, and compete better with Apple’s successful Mac transition to ARM. Since mobile laptops account for a larger share of personal computers (a 4:1 ratio), Microsoft has had no choice but to push Windows for ARM to combat Apple’s growing market share, which accelerated after Apple Silicon arrived in 202o.
(35) Spatial first supports ARM support for Apple Silicon for its Mac SDKs back in its 2023.1.0 release. It has now added ARM support for Linux, which will contribute to datacenter app support. Parasolid has supported ARM chip support for much longer, starting with Android ARM in version 31.1 and then Apple Silicon for Mac in version 33.1 (June 2021). Russian C3D Labs also added ARM support to its modeling kernel in June of 2025, with versions of ARM for macOS and Android.
Rhinoceros 3D (Rhino 3D) has an in-house geometry kernel (engine) that is built around the Non-Uniform Rational B-Spline (NURBS) mathematical model. The company fully supports Apple Silicon at the ARM chip level. It also supports Windows on ARM at the kernel level, though OpenGL driver issues do exist. Graphisoft has its own geometry engine as well and is Apple Silicon native. And Autodesk’s proprietary geometry kernels support macOS on Apple Silicon for products like AutoCAD for Mac and Fusion 360.
Heterogeneous Compute: GPU Geometry, AI Inference, Hybrid Evaluation
(36) Exploring ARM-based SoC & Heterogeneous Compute Architecture — Druva
This article describes the ARM big.LITTLE technology germane to the architecture. Here is a quote:
ARM big.LITTLE technology is a heterogeneous processing architecture that uses two different types of processors arranged as two clusters. Each cluster contains the same type of processor. The ”LITTLE” processors are designed for maximum power efficiency, while the ”big” processors are designed to provide maximum compute performance.
It is key to recognize that companies like Arm have spent decades refining the integration of diverse components into efficient Systems-on-Chip (SoCs). The big.LITTLE architecture has evolved into DynamicIQ architecture as total cores have scaled, which combines high-performance and high-efficiency CPU cores with shared memory access, a fundamental basis of heterogeneous design principles.
(37) What Happens After Semiconductor Scaling Laws Are Broken — Cadence
(38) What are the reasons for Arm based chips outperforming existing x86 chips in performance per watt — Reddit
(39) Why Apple Silicon is Better — Medium
This article is from a microprocessor architect who documented his considerations for which laptop to buy. The most interesting aspect of this article is the focus on data that came from the Ahashi Linux group of developers, who are working on running a Linux kernel natively on Apple Silicon and are optimizing their kernel for the M-series hardware by reverse-engineering Apple Silicon. As such, it contains details of the M1’s GLC architecture, which is not easy information to obtain, says the author.
(40) Qualcomm Snapdragon Takes Aim At PC Rivals Intel, AMD And Apple — Cambrian AI Research
“The laptop X2 Elite and X2 Elite Extreme, like the 1st generation of compute SoCs, come complete with Adreno GPU and Hexagon NPU cores that deliver the application performance needed for gaming and AI. The NPU can now deliver 80 Trillion Operations Per Second (TOPS), which is 78% faster than Gen 1, making it the fastest NPU in the industry.”
The article makes the point that both Qualcomm and Microsoft are focusing a lot of engineering effort on the emerging AI PC market, and Qualcomm’s NPU is the critical part of the heterogeneous ARM chip to handle this.
(41) AU25: All About Autodesk’s AI Neural CAD Engines — Architosh
“These new neural CAD engines are capable of creating CAD geometry from a multi-input system-level approach. At the same time, unlike the 3D graphics that today’s AI systems, such as ChatGPT, can produce, Autodesk’s new neural CAD engines generate CAD geometry that is fully editable using traditional parametric CAD inputs as well.”
Autodesk’s Neural CAD engines (of which we saw two at AU25) utilize “inference” based compute. One of the key things Autodesk is doing is teaching its AI foundation models to “reason with CAD geometry.” This requires training (executed on big data using GPUs at hyperscalers, no doubt) versus what end users will do, “inference,” which is the reasoning itself. However, we note that Autodesk said to the press that further down the road, organizations would be able to train AI models on their own proprietary data.
The Future of BIM: The Silicon Will Decide
(42) At 19:45 on this YouTube video, Jim Keller talks about ISAs, comparing ARM ISA to x86 ISA. Keller says, “For a while we thought variable length instructions were hard to decode, but we keep figuring out how to do that.” Keller then goes on to say that if you are building a really big chip, the prediction part isn’t really dominating the die. In other words, it’s an increasingly smaller part of the die. He also noted that when RISC came out, half the chip on x86 chips was a ROM and was microcoded. But today the ROM is very tiny.